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cpc700 memory controller and pci bridge cpc700 7/14/03 ?bm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 1 of 22 features powerpc 60x/7xx bus. 66.66 mhz 83.33 mhz synchronous dram interface operates at the processor bus speed with support for ecc. pci revision 2.1 compliant interface. rom/sram/external peripheral controller. interrupt controller supports interrupts from a variety of sources. programmable timers. two 2-wire, 8-bit, 16550 compatible uarts. two independent iic interfaces. byte swapping supported for bi-endian opera- tion. internal pci bus arbiter for pci bus speeds up to 33.33 mhz (may be disabled for use with an external arbiter). 32-bit pci bus operates at frequencies from 25mhz to 66.66 mhz. uses standard type 0 pci con?uration register map essential to making it appear like a device but does not preclude it from being a host. supports independent primary and secondary resource management mapping. this feature enables the cpc700 to effectively isolate local processing resources from host side memory and i/o allocations. through the use of three independent translation decodes, the powerpc operating environment access to pci is man- aged solely by the powerpc. dual address capabilities enhance the cpc700s capabilities by allowing it to manage, control, or test beyond 4gb limitations. support for shared memory is locally mapped to the processors rom or sdram through pci standard base address registers. two memory i/o bars are available for requesting host memory or i/o resources and managing pci to powerpc access. provides a special interface enabling the cpc700 to generate any pci command, includ- ing type 1 con?uration cycles. fully buffers pci writes and supports pci read pre-fetching from local memory. hardware enforces cache coherency. implemented in cmos5se. .
cpc700 memory controller and pci bridge ?bm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 2 of 22 cpc700 7/14/03 contents section 1. ?escription ....................................................................................................... 3 section 2. ?lectrical characteristics.................................................................................. 4 section 3. ?ignal lists..................................................................................................... 1 2 section 4. ?ackage information ...................................................................................... 18 section 5. ?rdering information ...................................................................................... 19
cpc700 memory controller and pci bridge cpc700 7/14/03 ?bm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 3 of 22 1. description the cpc700 contains a bridge from the powerpc processor to the pci bus, as well as a high-speed memory controller, internal peripherals, and control for external rom and external peripherals. the cpc700 is a gen- eral purpose solution for interfacing the high performance, superscalar, powerpc 603e, 740, and 750 families of risc microprocessors to a pci bus and system memory. cpc700 embedded bridge functional block diagram processor sdram ecc rom peripherals 1/2x opb bridge uart uart iic iic gpt (timers) 66.66 or 83.33 mhz processor local bus (plb) 33.33 mhz on chip peripheral bus (opb) 119 104 2 2 2 2 12 1 9 52 pci jtag misc. uic (interrupts) dcr bus system 5 25 to 66.66 mhz pci bus pll & cpc700 asic interface interface 66.66 or 83.33 mhz processor bus 8 parity or arbiter pci arb data parity
cpc700 memory controller and pci bridge ?bm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 4 of 22 cpc700 7/14/03 2. electrical characteristics absolute maximum ratings characteristic symbol value unit supply voltage v dd 0 to 3.6 v pll0 supply voltage av dd0 0 to 3.6 v pll1 supply voltage av dd1 0 to 3.6 v input voltage v in 0 to 3.6 v storage temperature range t stg -65 to 150 c recommended dc operating conditions parameter symbol min typ max unit notes supply voltage v dd 3.135 3.3 3.465 v pll0 supply voltage v dd 3.135 3.3 3.465 v pll1 supply voltage v dd 3.135 3.3 3.465 v input logic high (3.3v receivers) v ih 2.0 v dd v input logic high (5.0v receivers) v ih 2.0 5.50 v input logic low v il 0.0 0.8 v output logic high v oh 2.4 v dd v output logic low v ol 0.0 0.4 v input leakage current group 1 i il1 ?110 a2 input leakage current group 2 i il2 400 a3 input leakage current group 3 i il3 -250 a4 input max allowable overshoot (3.3v receivers) v imao3 v dd + 0.6 v input max allowable overshoot (5.0v receivers) v imao5 5.50 v input max allowable undershoot (3.3v receivers) v imau3 -0.60 v input max allowable undershoot (5.0v receivers) v imau5 -0.60 v output max allowable overshoot (3.3v receivers) v omao3 v dd + 0.6 v output max allowable overshoot (5.0v receivers) v omao5 5.50 v output max allowable undershoot (3.3v receivers) v omau3 -0.60 v die junction temperature t j -40 105 c 1. refer to the output signal power ranges table for power information. 2. input leakage currents for all inputs except those indicated in notes 3 and 4. 3. input leakage current for signals test_enable, gbl_n, tsiz[0], tsiz[1], tt[0], and tt[4]. 4. input leakage current for signals tsiz[2], tt[1], trst_n, tdi, tms, tck, di1, and di2. 5. in addition to any other speci?ation herein, all cpc700 pci bus i/os meet or exceed the pci v2.1 requirements for 3.3v and 5.0v signalling environments.
cpc700 memory controller and pci bridge cpc700 7/14/03 ?bm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 5 of 22 capacitance parameter symbol min max unit notes input capacitance group 1 cin1 5 pf 1, 3 input capacitance group 1 cin2 8 pf 2, 3 1. group 1 includes all signals except those indicated in note 2. 2. group 2 includes gbl_n, tsiz[0], tsiz[1], tt[4], and tt[0]. 3. excludes test signals test_enable, di1_n, di2_n, ri_n, and jtag signals. dc electrical characteristics parameter symbol min typ max unit notes thermal resistance, junction to ambient 15 c/w 1 thermal resistance, junction to balls 5.9 c/w 1,2 active operating current i dd 420 (66.66 mhz) 500 (83.33 mhz) ma 3 pll0 voltage v pll0 3.135 3.3 3.465 v pll0 vdd input current i pll0 14 ma pll1 voltage v pll1 3.135 3.3 3.465 v pll1 vdd input current i pll1 14 ma 1. under normal operating conditions, the cpc700 does not require a heat sink. 2. measured from junction to outside corner ball. 3. i dd max is measured at tc = 105 c, worst case operating conditions for frequency and voltage, and a capacitive load of 50 pf. power power processor/memory frequency units notes 66.66 83.33 mhz typical 1.1 1.2 w 1, 2 maximum 1.6 1.9 w 2, 3, 4 1. typical power is measured at vdd=3.3v, 27 c in a system executing typical sequences. 2. guaranteed by design and characterization and is not tested. 3. maximum power is measured at vdd=3.6v, 120 c in a system executing worse case sequences with the cpu caches disabled 4. maximum power at ?40 c can be derived by subtracting 0.05 w from the maximum power number at 120 c.
cpc700 memory controller and pci bridge ?bm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 6 of 22 cpc700 7/14/03 common i/o speci?ations for 66.66mhz and 83.33mhz (part 1 of 3) signal i/o input (ns) output (ns) output current (ma) clock notes setup time (min) hold time (min) valid delay (max) hold time (min) i/o h (max) i/o l (min) pci bus asynchronous operation 1, 2, 3, 5, 7 ad[0:31] i/o 1.6 0.0 5.6 1.6 16.8 14 pci (a) c/be_n[0:3] i/o 2.6 0.0 5.7 1.7 16.8 14 pci (a) devsel_n i/o 2.9 0.0 5.8 1.6 16.8 14 pci (a) frame_n i/o 2.9 0.0 5.6 1.8 16.8 14 pci (a) idsel i 1.8 0.0 pci (a) irdy_n i/o 2.8 0.0 5.3 1.7 16.8 14 pci (a) par i/o 2.3 0.0 5.3 1.8 16.8 14 pci (a) perr_n i/o 1.8 0.0 5.4 1.7 16.8 14 pci (a) rst_n o n/a n/a 13.4 9 stop_n i/o 2.7 0.0 5.8 1.7 16.8 14 pci (a) trdy_n i/o 2.6 0.0 5.8 1.7 16.8 14 pci (a) serr_n o 5.8 1.7 16.8 14 pci (a) pci bus 2:1 synchronous operation 1, 2, 4, 5, 7 ad[0:31] i/o 3.8 0.0 8.7 2.9 16.8 14 pci (s) c/be_n[0:3] i/o 5.5 0.0 8.6 2.8 16.8 14 pci (s) devsel_n i/o 4.8 0.0 8.4 2.8 16.8 14 pci (s) frame_n i/o 5.2 0.0 8.3 2.8 16.8 14 pci (s) idsel i 2.5 0.0 16.8 14 pci (s) irdy_n i/o 5.2 0.0 7.9 2.8 16.8 14 pci (s) par i/o 4.7 0.0 8.5 2.8 pci (s) perr_n i/o 4.1 0.0 8.8 3.1 16.8 14 pci (s) stop_n i/o 3.6 0.0 8.5 2.9 16.8 14 pci (s) trdy_n i/o 4.6 0.0 8.5 2.9 16.8 14 pci (s) serr_n o 8.3 2.3 16.8 14 pci (s) 1. timing is guaranteed by design and characterization and is not tested. 2. all i/o timing (cpu, pci, and other) is speci?d into a 50pf load. all timings include errors (if any) induced by internal plls, given a clock input with no jitter. sys (2x): timings shown are referenced to the rising edge of the output of pll0, operating at twice the frequency of the sys_clk input. pll0 locks to the rising edge of sys_clk. sys (1x): timing is referenced to sys_clk. pci (a): pci interface in asynchronous mode. timings are referenced to the pci_clk input. logic is clocked by the output of pll1, which repeats pci_clk. pci (s): pci interface in synchronous mode. timings are referenced to the sys_clk, which is assumed to be exactly equal to the pci clock. 3. asynchronous pci timings re?ct 66.66 mhz pci operation. output timings are speci?d into a 50pf load. 4. pci in 2:1 (cpu @ 66.66mhz, pci @ 33.33 mhz). 5. all pci timings meet or exceed pci v2.1 speci?ations. system designers should design using the pci timing budgets of the pci version 2.1 speci?ations. output delays are speci?d into a 50pf lumped load model. 6. iic output timing speci?d into a 250pf load. 7. this is a 5.0v receiver. other receivers are 3.3v receivers.
cpc700 memory controller and pci bridge cpc700 7/14/03 ?bm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 7 of 22 pci arbitration 1, 2, 5 gnt0_n/req_n o 8.8 2.7 16.8 14 pci (a) async internal arbiter 9.3 2.9 16.8 14 pci (s) sync internal arbiter 5.3 1.7 16.8 14 pci (a) async external arbiter 7.6 2.6 16.8 14 pci (s) sync external arbiter req0_n/gnt_n i 4.7 0.0 pci (a) async internal arbiter 4.7 0.0 sys (s) sync internal arbiter 2.7 0.0 pci (a) async external arbiter 5.1 0.0 pci (s) sync external arbiter req[1:5]_n i 4.4 0.0 pci (a) async internal arbiter 4.4 0.0 pci (s) sync internal arbiter gnt[1:5]_n o 8.8 2.7 16.8 14 pci (a) async internal arbiter 9.3 2.9 16.8 14 pci (s) sync internal arbiter common i/o speci?ations for 66.66mhz and 83.33mhz (part 2 of 3) signal i/o input (ns) output (ns) output current (ma) clock notes setup time (min) hold time (min) valid delay (max) hold time (min) i/o h (max) i/o l (min) 1. timing is guaranteed by design and characterization and is not tested. 2. all i/o timing (cpu, pci, and other) is speci?d into a 50pf load. all timings include errors (if any) induced by internal plls, given a clock input with no jitter. sys (2x): timings shown are referenced to the rising edge of the output of pll0, operating at twice the frequency of the sys_clk input. pll0 locks to the rising edge of sys_clk. sys (1x): timing is referenced to sys_clk. pci (a): pci interface in asynchronous mode. timings are referenced to the pci_clk input. logic is clocked by the output of pll1, which repeats pci_clk. pci (s): pci interface in synchronous mode. timings are referenced to the sys_clk, which is assumed to be exactly equal to the pci clock. 3. asynchronous pci timings re?ct 66.66 mhz pci operation. output timings are speci?d into a 50pf load. 4. pci in 2:1 (cpu @ 66.66mhz, pci @ 33.33 mhz). 5. all pci timings meet or exceed pci v2.1 speci?ations. system designers should design using the pci timing budgets of the pci version 2.1 speci?ations. output delays are speci?d into a 50pf lumped load model. 6. iic output timing speci?d into a 250pf load. 7. this is a 5.0v receiver. other receivers are 3.3v receivers.
cpc700 memory controller and pci bridge ?bm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 8 of 22 cpc700 7/14/03 irq [0:11], reset_n, and pci_66_strap are asynchronous inputs that use 5.0v receivers. timing to the clock and output characteristics are not specified for these pins. there is an internal 13k ? pull-down resistor connected to pin test_enable. there are internal 13k ? pull-down resistors connected to pins gbl_n, tsiz [0:1], tt [0], and tt [4]. there are internal 20k ? pull-up resistors connected to pins tsiz [2] and tt [1]. rom interface rom_ale o 12.1 4.5 10.2 6.8 sys (2x) rom_oe_n o 8.1 2.8 19 16 sys (2x) rom_rd_n o 9.0 3.3 13.4 9 sys (2x) 7 rom_ready i 3.5 1.0 sys (2x) rom_rnw o 8.6 3.1 13.4 9 sys (2x) rom_we_n o 7.8 2.8 19 16 sys (2x) rom_wr_n o 9.0 3.3 13.4 9 sys (2x) iic port iic_scl i/o 3.0 1.0 22.7 4.3 13.4 9 sys (1x) 6, 7 iic_sda i/o 2.0 1.0 21.6 4.3 13.4 9 sys (1x) 6, 7 uart ports uart_rx i 2.5 1.0 sys (1x) uart_tx o 11.1 3.9 10.2 6.8 sys (1x) miscellaneous reset_out_n o 19 16 sys (2x) irq_out_n o 10.2 6.8 tdo o 10.2 6.8 common i/o speci?ations for 66.66mhz and 83.33mhz (part 3 of 3) signal i/o input (ns) output (ns) output current (ma) clock notes setup time (min) hold time (min) valid delay (max) hold time (min) i/o h (max) i/o l (min) 1. timing is guaranteed by design and characterization and is not tested. 2. all i/o timing (cpu, pci, and other) is speci?d into a 50pf load. all timings include errors (if any) induced by internal plls, given a clock input with no jitter. sys (2x): timings shown are referenced to the rising edge of the output of pll0, operating at twice the frequency of the sys_clk input. pll0 locks to the rising edge of sys_clk. sys (1x): timing is referenced to sys_clk. pci (a): pci interface in asynchronous mode. timings are referenced to the pci_clk input. logic is clocked by the output of pll1, which repeats pci_clk. pci (s): pci interface in synchronous mode. timings are referenced to the sys_clk, which is assumed to be exactly equal to the pci clock. 3. asynchronous pci timings re?ct 66.66 mhz pci operation. output timings are speci?d into a 50pf load. 4. pci in 2:1 (cpu @ 66.66mhz, pci @ 33.33 mhz). 5. all pci timings meet or exceed pci v2.1 speci?ations. system designers should design using the pci timing budgets of the pci version 2.1 speci?ations. output delays are speci?d into a 50pf lumped load model. 6. iic output timing speci?d into a 250pf load. 7. this is a 5.0v receiver. other receivers are 3.3v receivers.
cpc700 memory controller and pci bridge cpc700 7/14/03 ?bm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 9 of 22 cpu and memory interface i/o speci?ations for 66.66 mhz signal i/o input (ns) output (ns) output current (ma) clock notes setup time (min) hold time (min) valid delay (max) hold time (min) i/o h (max) i/o l (min) cpu bus interface 1, 2 a[0:31] i/o 3.0 1.0 10.3 3.5 sys (2x) aack_n o 9.3 3.5 10.2 6.8 sys (2x) ap[0:3] i/o 2.5 1.0 9.4 3.4 16.8 14 sys (2x) artry_n i/o 2.5 1.0 8.5 3.2 10.2 6.8 sys (2x) bg_n o 8.5 3.2 10.2 6.8 sys (2x) br_n i 3.0 1.0 sys (2x) dbg_n o 9.5 3.5 10.2 6.8 sys (2x) dh[0:31] i/o 3.0 1.0 9.6 3.4 10.2 6.8 sys (2x) dl[0:31] i/o 3.0 1.0 9.8 3.5 10.2 6.8 sys (2x) dp[0:7] i/o 2.5 1.0 6.1 1.8 16.8 14 sys (2x) 3 gbl_n o 9.5 3.5 10.2 6.8 sys (2x) 6 mcp_n o 10.3 3.9 10.2 6.8 sys (2x) 4 mcp_req i 2.5 1.0 sys (2x) 3 ta_n o 9.1 3.2 10.2 6.8 sys (2x) tbst_n i/o 2.5 1.0 10.1 3.6 10.2 6.8 sys (2x) 5 ts_n i/o 3.0 1.7 8.6 2.9 10.2 6.8 sys (2x) tsiz[0:2] i/o 2.5 1.0 9.8 3.5 10.2 6.8 sys (2x) tt[0:4] i/o 2.5 1.0 9.3 3.5 10.2 6.8 sys (2x) memory controller interface 1, 2 ba0 o 11.1 2.8 19 16 sys (2x) ba1 o 10.6 2.8 19 16 sys (2x) bank_sel_n[0:4] o 8.1 2.8 13.4 9 sys (2x) cas_n o 6.6 2.4 19 16 sys (2x) cke o 6.8 2.4 19 16 sys (2x) m_data[0:63] i/o 3.0 1.0 7.8 2.8 13.4 9 sys (2x) dqm[0] o 6.9 2.5 19 16 sys (2x) ecc[0] i/o 3.0 1.0 8.0 2.9 13.4 9 sys (2x) ecc[1:7]/dqm[1:7] i/o 3.0 1.0 8.0 2.9 13.4 9 sys (2x) ma[0:12] o 11.1 3.0 19 16 sys (2x) ras_n o 6.9 2.4 19 16 sys (2x) we_n o 6.7 2.4 19 16 sys (2x) 1. timing is guaranteed by design and characterization and is not tested. 2. all i/o timing (cpu, pci, and other) is speci?d into a 50pf load. all timings include errors (if any) induced by internal plls, given a clock input with no jitter. sys (2x): timings shown are referenced to the rising edge of the output of pll0, operating at twice the frequency of the sys_clk input. pll0 locks to the rising edge of sys_clk. sys (1x): timing is referenced to sys_clk. pci (a): pci interface in asynchronous mode. timings are referenced to the pci_clk input. logic is clocked by the output of pll1, which repeats pci_clk. pci (s): pci interface in synchronous mode. timings are referenced to the sys_clk, which is assumed to be exactly equal to the pci clock... 3. this is a 5.0v receiver. other receivers are 3.3v receivers 4. this output mimics an open collector gate and requires a pull-up resistor. 5. tbst_n is never driven low. tbst_n is driven high on snoops. 6. gbl_n is not sampled.
cpc700 memory controller and pci bridge ?bm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 10 of 22 cpc700 7/14/03 cpu and memory interface i/o speci?ations for 83.33 mhz signal i/o input (ns) output (ns) output current (ma) clock notes setup time (min) hold time (min) valid delay (max) hold time (min) i/o h (max) i/o l (min) cpu bus interface 1, 2 a[0:31] i/o 2.5 1.0 6.6 3.5 sys (2x) aack_n o 6.5 3.5 10.2 6.8 sys (2x) ap[0:3] i/o 2.5 1.0 6.6 3.4 16.8 14 sys (2x) artry_n i/o 2.5 1.0 6.0 3.2 10.2 6.8 sys (2x) bg_n o 6.0 3.2 10.2 6.8 sys (2x) br_n i 2.5 1.0 sys (2x) dbg_n o 6.7 3.5 10.2 6.8 sys (2x) dh[0:31] i/o 3.0 1.0 7.1 3.4 10.2 6.8 sys (2x) dl[0:31] i/o 3.0 1.0 7.1 3.5 10.2 6.8 sys (2x) dp[0:7] i/o 2.5 1.0 6.1 1.8 16.8 14 sys (2x) 3 gbl_n o 7.2 3.5 10.2 6.8 sys (2x) 6 mcp_n o 7.8 3.9 10.2 6.8 sys (2x) 4 mcp_req i 2.5 1.0 sys (2x) 3 ta_n o 6.0 3.2 10.2 6.8 sys (2x) tbst_n i/o 2.5 1.0 7.6 3.6 10.2 6.8 sys (2x) 5 ts_n i/o 2.5 1.0 6.0 2.9 10.2 6.8 sys (2x) tsiz[0:2] i/o 2.5 1.0 6.7 3.5 10.2 6.8 sys (2x) tt[0:4] i/o 2.1 1.0 7.0 3.5 10.2 6.8 sys (2x) memory controller interface 1, 2 ba0 o 9.0 2.8 19 16 sys (2x) ba1 o 8.5 2.8 19 16 sys (2x) bank_sel_n[0:4] o 6.0 2.8 13.4 9 sys (2x) cas_n o 5.9 2.4 19 16 sys (2x) cke o 5.8 2.4 19 16 sys (2x) m_data[0:63] i/o 2.5 1.0 6.0 2.8 13.4 9 sys (2x) dqm[0] o 5.7 2.5 19 16 sys (2x) ecc[0] i/o 2.5 1.0 6.0 2.9 13.4 9 sys (2x) ecc[1:7]/dqm[1:7] i/o 2.5 1.0 6.0 2.9 13.4 9 sys (2x) ma[0:12] o 8.9 3.0 19 16 sys (2x) ras_n o 5.8 2.4 19 16 sys (2x) we_n o 5.7 2.4 19 16 sys (2x) 1. timing is guaranteed by design and characterization and is not tested. 2. all i/o timing (cpu, pci, and other) is speci?d into a 50pf load. all timings include errors (if any) induced by internal plls, given a clock input with no jitter. sys (2x): timings shown are referenced to the rising edge of the output of pll0, operating at twice the frequency of the sys_clk input. pll0 locks to the rising edge of sys_clk. sys (1x): timing is referenced to sys_clk. pci (a): pci interface in asynchronous mode. timings are referenced to the pci_clk input. logic is clocked by the output of pll1, which repeats pci_clk. pci (s): pci interface in synchronous mode. timings are referenced to the sys_clk, which is assumed to be exactly equal to the pci clock. 3. this is a 5.0v receiver. other receivers are 3.3v receivers. 4. this output mimics an open collector gate and requires a pull-up resistor. 5. tbst_n is never driven low. tbst_n is driven high on snoops. 6. gbl_n is not sampled.
cpc700 memory controller and pci bridge cpc700 7/14/03 ?bm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 11 of 22 clock dc speci?ations signal name minimum vih maximum vil cin sys_clk 2.0v 0.8v 5pf pci_clk 2.0v 0.8v 5pf cpc700 - 66 clock ac speci?ations signal name input jitter duty cycle fmin fmax short long min max notes sys_clk 30 mhz 33.33mhz 150ps 250ps 40% 60% 3 pci_clk 25 mhz 66.66mhz 150ps 250ps 40% 60% 1. in the clock tables, 25 mhz represents 1/(40ns), 33.33mhz represents 1/(30ns), 41.66mhz represents 1/(24ns), 66.66mhz repre- sents 1/(15ns), and 83.33mhz represents 1/(12ns). 2. for information on cpc700 operation with a spread spectrum clock, please contact your ibm technical representative. cpc700 - 83 clock ac speci?ations signal name input jitter duty cycle fmin fmax short long min max notes sys_clk 30mhz 41.66mhz 150ps 250ps 40% 60% 3 pci_clk 25mhz 66.66mhz 150ps 250ps 40% 60% 1. in the clock tables, 25mhz represents 1/(40ns), 33.33mhz represents 1/(30ns), 41.66mhz represents 1/(24ns), 66.66mhz repre- sents 1/(15ns), and 83.33mhz represents 1/(12ns). 2. for information on cpc700 operation with a spread spectrum clock, please contact your ibm technical representative. 3. in previous versions of this data sheet, sys_clk fmin was incorrectly listed as 10 mhz.
cpc700 memory controller and pci bridge ?bm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 12 of 22 cpc700 7/14/03 3. signal lists pin number list (part 1 of 9) pin signal a01 no ball a02 ecc7/dqm7 a03 ecc5/dqm5 a04 m_data63 a05 m_data61 a06 unused a07 m_data59 a08 unused a09 m_data41 a10 unused a11 m_data26 a12 unused a13 m_data22 a14 unused a15 m_data08 a16 m_data01 a17 bank_sel_n2 a18 bank_sel_n1 a19 gnd aa01 ad03 aa02 gnd aa03 vdd aa04 a02 aa05 a16 aa06 vdd aa07 dl06 aa08 gnd aa09 dl22 aa10 vdd aa11 dh08 aa12 gnd aa13 dh13 aa14 vdd aa15 dp7/gnt5_n aa16 dh25 aa17 ap3 aa18 gnd aa19 a31 ab01 ad00 ab02 ad01 ab03 a06 ab04 a10 ab05 a24 ab06 dl01 ab07 dl08 ab08 dl18 ab09 dl11 ab10 dh05 ab11 dh06 ab12 dh19 ab13 dh12 ab14 dh17 ab15 dh21 ab16 dh29 ab17 a27 ab18 dl25 ab19 ap0 ac01 a00 ac02 a08 ac03 a04 ac04 vdd ac05 dl04 ac06 dl07 ac07 dh02 ac08 vdd ac09 dl17 ac10 dp1/req3_n ac11 dh07 ac12 vdd ac13 ri ac14 dh18 ac15 dh24 ac16 vdd ac17 dl29 ac18 dl23 ac19 dl28 ad01 a14 ad02 a12 ad03 a20 ad04 a28 ad05 dp3/req5_n ad06 gnd ad07 dh03 ad08 dl10 ad09 dh00 ad10 gnd ad11 dh14 ad12 dp2/req4_n ad13 dp5/gnt3_n ad14 gnd ad15 dh26 ad16 dh28 ad17 dl31 ad18 dl24 ad19 dl27 ae01 gnd ae02 a22 ae03 a26 ae04 a30 ae05 dl02 ae06 unused ae07 dh09 ae08 unused ae09 dh10 ae10 unused ae11 dh11 ae12 unused ae13 dh27 pin number list (part 2 of 9) pin signal ae14 unused ae15 dh30 ae16 dh31 ae17 dl30 ae18 dl26 ae19 gnd b01 uart0_tx b02 ecc6/dqm6 b03 ecc4/dqm4 b04 m_data62 b05 m_data60 b06 gnd b07 m_data47 b08 m_data42 b09 m_data39 b10 gnd b11 m_data25 b12 m_data21 b13 m_data23 b14 gnd b15 m_data00 b16 m_data02 b17 bank_sel_n3 b18 bank_sel_n0 b19 cke c01 uart0_rx c02 uart1_tx c03 ecc1/dqm1 c04 vdd c05 m_data54 c06 m_data55 c07 m_data45 c08 vdd c09 m_data35 c10 vdd c11 m_data27 c12 vdd c13 m_data13 c14 m_data09 c15 m_data03 c16 vdd c17 bank_sel_n4 c18 cas_n c19 ras_n d01 irq0 d02 uart1_rx d03 ecc0 d04 ecc2/dqm2 d05 m_data58 d06 m_data46 d07 m_data44 d08 m_data40 d09 m_data36 d10 m_data31 pin number list (part 3 of 9) pin signal
cpc700 memory controller and pci bridge cpc700 7/14/03 ?bm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 13 of 22 d11 m_data17 d12 m_data19 d13 m_data12 d14 m_data11 d15 m_data04 d16 unused d17 ma11 d18 we_n d19 dqm0 e01 irq02 e02 gnd e03 iic0_scl e04 ecc3/dqm3 e05 m_data57 e06 vdd e07 m_data43 e08 gnd e09 m_data34 e10 vdd e11 m_data18 e12 gnd e13 m_data15 e14 vdd e15 m_data05 e16 m_data06 e17 ma06 e18 gnd e19 ma09 f01 unused f02 iic1_scl f03 iic1_sda f04 iic0_sda f05 m_data56 f06 unused f07 gnd f08 m_data32 f09 m_data33 f10 m_data30 f11 m_data24 f12 m_data20 f13 m_data14 f14 m_data10 f15 m_data07 f16 ma03 f17 ma05 f18 ma07 f19 unused g01 irq05 g02 gnd g03 irq01 g04 vdd g05 irq04 g06 gnd g07 unused g08 vdd g09 unused pin number list (part 4 of 9) pin signal g10 gnd g11 unused g12 vdd g13 unused g14 gnd g15 rom_rd_n g16 vdd g17 ma04 g18 ma10/ap g19 ma08 h01 pcipll_vdda h02 irq06 h03 pci_clk h04 vdd h05 irq03 h06 unused h07 unused h08 unused h09 m_data53 h10 m_data38 h11 m_data16 h12 unused h13 unused h14 rom_ale h15 unused h16 ma02 h17 ma01 h18 ma00 h19 ma12 j01 unused j02 vdd j03 irq08 j04 gnd j05 irq10 j06 vdd j07 unused j08 gnd j09 m_data52 j10 vdd j11 m_data29 j12 gnd j13 unused j14 vdd j15 unused j16 gnd j17 ba1 j18 vdd j19 unused k01 rst_n k02 irq11 k03 tms k04 req0_n/gnt_n k05 gnt1_n k06 irq09 k07 unused k08 m_data49 pin number list (part 5 of 9) pin signal k09 m_data51 k10 m_data37 k11 m_data28 k12 rom_oe_n k13 unused k14 unused k15 rom_wr_n k16 rom_rnw k17 tdo k18 ba0 k19 sys_reset_n l01 unused l02 devsel_n l03 par l04 vdd l05 irq07 l06 gnd l07 idsel l08 vdd l09 m_data50 l10 gnd l11 gnd l12 vdd l13 rom_ready l14 gnd l15 rom_we_n l16 vdd l17 reset_out_n l18 pci_66_strap l19 unused m01 ad28 m02 ad20 m03 req1_n m04 ad30 m05 ad31 m06 serr_n m07 gnt0_n/req_n m08 perr_n m09 vdd m10 m_data48 m11 vdd m12 dbg_n m13 ta_n m14 aack_n m15 test_enable m16 mcp_n m17 sys_clk m18 gnd m19 syspll_vdda n01 ad19 n02 vdd n03 ad27 n04 gnd n05 ad26 n06 vdd n07 frame_n pin number list (part 6 of 9) pin signal
cpc700 memory controller and pci bridge ?bm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 14 of 22 cpc700 7/14/03 n08 gnd n09 ad29 n10 gnd n11 tsiz2 n12 gnd n13 tsiz1 n14 vdd n15 br_n n16 gnd n17 gbl_n n18 vdd n19 mcp_req p01 c/be_n0 p02 ad21 p03 tck p04 irdy_n p05 ad23 p06 trdy_n p07 ad24 p08 ad11 p09 vdd p10 ad25 p11 vdd p12 artry_n p13 irq_out_n p14 ts_n p15 tt3 p16 tsiz0 p17 tdi p18 vdd p19 trst_n r01 ad15 r02 ad17 r03 ad18 r04 vdd r05 ad14 r06 gnd r07 unused r08 vdd r09 dl03 r10 gnd r11 dl12 r12 vdd r13 a23 r14 gnd r15 tt0 r16 vdd r17 bg_n r18 tt4 r19 tbst_n t01 ad13 t02 c/be_n1 t03 ad16 t04 stop_n t05 ad12 t06 unused pin number list (part 7 of 9) pin signal t07 unused t08 c/be_n3 t09 dl14 t10 dl13 t11 dl09 t12 dl19 t13 unused t14 a01 t15 a21 t16 ap1 t17 a07 t18 tt1 t19 tt2 u01 unused u02 vdd u03 ad22 u04 gnd u05 unused u06 vdd u07 unused u08 gnd u09 unused u10 vdd u11 dl05 u12 gnd u13 unused u14 vdd u15 unused u16 gnd u17 a03 u18 vdd u19 unused v01 di1_n v02 ad09 v03 di2_n v04 ad10 v05 c/be_n2 v06 unused v07 unused v08 unused v09 dl16 v10 dh04 v11 dl00 v12 dh16 v13 unused v14 unused v15 a09 v16 ap2 v17 a11 v18 a13 v19 a05 w01 ad08 w02 ad07 w03 ad06 w04 vdd w05 unused pin number list (part 8 of 9) pin signal w06 gnd w07 unused w08 vdd w09 dp0/req2_n w10 gnd w11 dh15 w12 vdd w13 unused w14 gnd w15 unused w16 vdd w17 a15 w18 a25 w19 a17 y01 unused y02 ad04 y03 ad05 y04 ad02 y05 a18 y06 unused y07 dp6/gnt4_n y08 dh01 y09 dl15 y10 dl20 y11 dl21 y12 dh20 y13 dh23 y14 unused y15 dh22 y16 dp4/gnt2_n y17 a19 y18 a29 y19 unused pin number list (part 9 of 9) pin signal
cpc700 memory controller and pci bridge cpc700 7/14/03 ?bm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 15 of 22 signal name list (part 1 of 9) pin signal ac01 a00 t14 a01 aa04 a02 u17 a03 ac03 a04 v19 a05 ab03 a06 t17 a07 ac02 a08 v15 a09 ab04 a10 v17 a11 ad02 a12 v18 a13 ad01 a14 w17 a15 aa05 a16 w19 a17 y05 a18 y17 a19 ad03 a20 t15 a21 ae02 a22 r13 a23 ab05 a24 w18 a25 ae03 a26 ab17 a27 ad04 a28 y18 a29 ae04 a30 aa19 a31 m14 aack_n ab01 ad00 ab02 ad01 y04 ad02 aa01 ad03 y02 ad04 y03 ad05 w03 ad06 w02 ad07 w01 ad08 v02 ad09 v04 ad10 p08 ad11 t05 ad12 t01 ad13 r05 ad14 r01 ad15 t03 ad16 r02 ad17 r03 ad18 n01 ad19 m02 ad20 p02 ad21 u03 ad22 p05 ad23 p07 ad24 p10 ad25 n05 ad26 n03 ad27 m01 ad28 n09 ad29 m04 ad30 m05 ad31 ab19 ap0 t16 ap1 v16 ap2 aa17 ap3 p12 artry_n k18 ba0 j17 ba1 b18 bank_sel_n0 a18 bank_sel_n1 a17 bank_sel_n2 b17 bank_sel_n3 c17 bank_sel_n4 r17 bg_n n15 br_n p01 c/be_n0 t02 c/be_n1 v05 c/be_n2 t08 c/be_n3 c18 cas_n b19 cke m12 dbg_n l02 devsel_n ad09 dh00 y08 dh01 ac07 dh02 ad07 dh03 v10 dh04 ab10 dh05 ab11 dh06 ac11 dh07 aa11 dh08 ae07 dh09 ae09 dh10 ae11 dh11 ab13 dh12 aa13 dh13 ad11 dh14 w11 dh15 v12 dh16 ab14 dh17 ac14 dh18 ab12 dh19 y12 dh20 ab15 dh21 y15 dh22 y13 dh23 signal name list (part 2 of 9) pin signal ac15 dh24 aa16 dh25 ad15 dh26 ae13 dh27 ad16 dh28 ab16 dh29 ae15 dh30 ae16 dh31 v01 di1_n v03 di2_n v11 dl00 ab06 dl01 ae05 dl02 r09 dl03 ac05 dl04 u11 dl05 aa07 dl06 ac06 dl07 ab07 dl08 t11 dl09 ad08 dl10 ab09 dl11 r11 dl12 t10 dl13 t09 dl14 y09 dl15 v09 dl16 ac09 dl17 ab08 dl18 t12 dl19 y10 dl20 y11 dl21 aa09 dl22 ac18 dl23 ad18 dl24 ab18 dl25 ae18 dl26 ad19 dl27 ac19 dl28 ac17 dl29 ae17 dl30 ad17 dl31 w09 dp0/req2_n ac10 dp1/req3_n ad12 dp2/req4_n ad05 dp3/req5_n y16 dp4/gnt4_n ad13 dp5/gnt3_n y07 dp6/gnt4_n aa15 dp7/gnt5_n d19 dqm0 d03 ecc0 c03 ecc1/dqm1 d04 ecc2/dqm2 e04 ecc3/dqm3 b03 ecc4/dqm4 signal name list (part 3 of 9) pin signal
cpc700 memory controller and pci bridge ?bm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 16 of 22 cpc700 7/14/03 a03 ecc5/dqm5 b02 ecc6/dqm6 a02 ecc7/dqm7 n07 frame_n n17 gbl_n a19 gnd aa02 gnd aa08 gnd aa12 gnd aa18 gnd ad06 gnd ad10 gnd ad14 gnd ae01 gnd ae19 gnd b06 gnd b10 gnd b14 gnd e02 gnd e08 gnd e12 gnd e18 gnd f07 gnd g02 gnd g06 gnd g10 gnd g14 gnd j04 gnd j08 gnd j12 gnd j16 gnd l06 gnd l10 gnd l11 gnd l14 gnd m18 gnd n04 gnd n08 gnd n10 gnd n12 gnd n16 gnd r06 gnd r10 gnd r14 gnd u04 gnd u08 gnd u12 gnd u16 gnd w06 gnd w10 gnd w14 gnd m07 gnt0_n/req_n k05 gnt1_n l07 idsel e03 iic0_scl f04 iic0_sda signal name list (part 4 of 9) pin signal f02 iic1_scl f03 iic1_sda p04 irdy_n d01 irq0 g03 irq01 e01 irq02 h05 irq03 g05 irq04 g01 irq05 h02 irq06 l05 irq07 j03 irq08 k06 irq09 j05 irq10 k02 irq11 p13 irq_out_n b15 m_data00 a16 m_data01 b16 m_data02 c15 m_data03 d15 m_data04 e15 m_data05 e16 m_data06 f15 m_data07 a15 m_data08 c14 m_data09 f14 m_data10 d14 m_data11 d13 m_data12 c13 m_data13 f13 m_data14 e13 m_data15 h11 m_data16 d11 m_data17 e11 m_data18 d12 m_data19 f12 m_data20 b12 m_data21 a13 m_data22 b13 m_data23 f11 m_data24 b11 m_data25 a11 m_data26 c11 m_data27 k11 m_data28 j11 m_data29 f10 m_data30 d10 m_data31 f08 m_data32 f09 m_data33 e09 m_data34 c09 m_data35 d09 m_data36 k10 m_data37 h10 m_data38 b09 m_data39 signal name list (part 5 of 9) pin signal d08 m_data40 a09 m_data41 b08 m_data42 e07 m_data43 d07 m_data44 c07 m_data45 d06 m_data46 b07 m_data47 m10 m_data48 k08 m_data49 l09 m_data50 k09 m_data51 j09 m_data52 h09 m_data53 c05 m_data54 c06 m_data55 f05 m_data56 e05 m_data57 d05 m_data58 a07 m_data59 b05 m_data60 a05 m_data61 b04 m_data62 a04 m_data63 h18 ma00 h17 ma01 h16 ma02 f16 ma03 g17 ma04 f17 ma05 e17 ma06 f18 ma07 g19 ma08 e19 ma09 g18 ma10/ap d17 ma11 h19 ma12 m16 mcp_n n19 mcp_req l03 par l18 pci_66_strap h03 pci_clk h01 pcipll_vdda m08 perr_n c19 ras_n k04 req0_n/gnt_n m03 req1_n l17 reset_out_n ac13 ri_n h14 rom_ale k12 rom_oe_n g15 rom_rd_n l13 rom_ready k16 rom_rnw l15 rom_we_n k15 rom_wr_n signal name list (part 6 of 9) pin signal
cpc700 memory controller and pci bridge cpc700 7/14/03 ?bm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 17 of 22 k01 rst_n m06 serr_n t04 stop_n m17 sys_clk k19 sys_reset_n m19 syspll_vdda m13 ta_n r19 tbst_n p03 tck p17 tdi k17 tdo m15 test_enable k03 tms p06 trdy_n p19 trst_n p14 ts_n p16 tsiz0 n13 tsiz1 n11 tsiz2 r15 tt0 t18 tt1 t19 tt2 p15 tt3 r18 tt4 c01 uart0_rx b01 uart0_tx d02 uart1_rx c02 uart1_tx a06 unused a08 unused a10 unused a12 unused a14 unused ae06 unused ae08 unused ae10 unused ae12 unused ae14 unused d16 unused f01 unused f06 unused f19 unused g07 unused g09 unused g11 unused g13 unused h06 unused h07 unused h08 unused h12 unused h13 unused h15 unused j01 unused j07 unused j13 unused j15 unused signal name list (part 7 of 9) pin signal j19 unused k07 unused k13 unused k14 unused l01 unused l19 unused r07 unused t06 unused t07 unused t13 unused u01 unused u05 unused u07 unused u09 unused u13 unused u15 unused u19 unused v06 unused v07 unused v08 unused v13 unused v14 unused w05 unused w07 unused w13 unused w15 unused y01 unused y06 unused y14 unused y19 unused aa03 vdd aa06 vdd aa10 vdd aa14 vdd ac04 vdd ac08 vdd ac12 vdd ac16 vdd c04 vdd c08 vdd c10 vdd c12 vdd c16 vdd e06 vdd e10 vdd e14 vdd g04 vdd g08 vdd g12 vdd g16 vdd h04 vdd j02 vdd j06 vdd j10 vdd j14 vdd j18 vdd signal name list (part 8 of 9) pin signal l04 vdd l08 vdd l12 vdd l16 vdd m09 vdd m11 vdd n02 vdd n06 vdd n14 vdd n18 vdd p09 vdd p11 vdd p18 vdd r04 vdd r08 vdd r12 vdd r16 vdd u02 vdd u06 vdd u10 vdd u14 vdd u18 vdd w04 vdd w08 vdd w12 vdd w16 vdd d18 we_n signal name list (part 9 of 9) pin signal
cpc700 memory controller and pci bridge ?bm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 18 of 22 cpc700 7/14/03 4. package information 474-pin cbga 0.15 c c 01 m solder ball x 474 c ? 0.3 ? 0.1 m c a b s s 19 index mark b a center line screening fiducials x 12 ( ? 0.1) chip placement fiducials x 2 fiducials x 4 a01 12.902 11.980 13.363 1.5 0.65 10.598 1.843 7.142 13.363 13.594 10.598 11.059 0.925 25 0.2 32.5 0.2 1.27 typ 1.07 0.1 3.15 0.9 0.1 3.05 max 2.5 min 1.01 0.1 13.824 (474x) ( ? 0.89 ?0.07 +0.04 ) top view bottom view abcde fghj kl mnprtuvw y aa ab ac ad ae 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18
cpc700 memory controller and pci bridge cpc700 7/14/03 ?bm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 19 of 22 5. ordering information for availability, contact your local ibm sales office. note 1: previous versions of this document contained an error in the oemls part numbers of the parts shown. the 45l7531, 09k4299, and 09k4298 part numbers showed a "b" in the application conditions ?ld, instead of "a", which is now shown correctly. all of these parts that were shipped by ibm were correctly marked. note 2: part number 45l7530 has a "b" in the oemls part number, and is marked with a "b" on the package and in all revisions of the datasheet. this part is actually speci?d for "a" application conditions. for this part number, decode the "b" to mean "full speci?ation." the oemls part number and package marking of 45l7530 will not be changed. this part number will not be issued with any other application conditions. oemls part number internal ibm part number processor bus frequency shipping package rev level ibm25cpc700bb3a66 1 45l7531 66.66 tray dd 1.1 ibm25cpc700bb3b83 2 45l7530 83.33 tray dd 1.1 ibm25cpc700cb3a66 1 09k4299 66.66 tray dd 1.2 ibm25cpc700cb3a83 1 09k4298 83.33 tray dd 1.2 ibm25cpc700db3a66 88h3097 66.66 tray dd 1.3 ibm25cpc700db3a66z 88h4076 66.66 tape and reel dd 1.3 IBM25CPC700DB3A83 88h3096 83.33 tray dd 1.3 IBM25CPC700DB3A83z 88h3990 83.33 tape and reel dd 1.3 .
cpc700 memory controller and pci bridge ?bm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 20 of 22 cpc700 7/14/03 the following figure provides the part numbering nomenclature for the cpc700. oemls part number key marketing part number IBM25CPC700DB3A83z package processor bus frequency reliability application conditions b a revision pci rev reg dd 1.1 dd 1.0 0000 0000 0000 0001 66 = 66.66 mhz 83 = 83.33 mhz a = full specification dd 1.2 c 0000 0010 code revision level d dd 1.3 0000 0011 shipping package blank = tray z = tape and reel 3= grade 3 b = cbga
cpc700 memory controller and pci bridge cpc700 7/14/03 ?bm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 21 of 22 inside of back cover
cpc700 memory controller and pci bridge ?bm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 22 of 22 cpc700 7/14/03 copyright ?nternational business machines corporation 2003 printed in the united states of america july 14, 2003 all rights reserved trademarks the following are trademarks of international business machines corporation in the united states, or other countries, or both: ibm, ibm logo, aix, cpc700, and powerpc. other company, product, and service names may be trademarks or service marks of others. all information contained in this document is subject to change without notice. the products described in this document are not intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. the information contained in this document does not affect or change ibms product speci?ations or warranties. nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of ibm or third parties. all information contained in this document was obtained in speci? environments, and is presented as illustration. the results obtained in other operating environments may vary. the information contained in this document is provided on an ?s is?basis. in no event will ibm be liable for any damages arising directly or indirectly from any use of the information contained in this document. ibm microelectronics division 1580 route 52, bldg. 504 hopewell junction, ny 12533-6531 the ibm home page can be found at http://www.ibm.com the ibm microelectronics division home page can be found at http://www.chips.ibm.com

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